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? semiconductor components industries, llc, 2015 august, 2015 ? rev. 5 1 publication order number: kai ? 01150/d kai-01150 1280 (h) x 720 (v) interline ccd image sensor description the on semiconductor kai ? 01150 image sensor is a 720p format (1280 x 720 pixel) ccd in a 1/2? optical format. based on the truesense 5.5 micron interline transfer ccd platform, the sensor features broad dynamic range, excellent imaging performance, and a flexible readout architecture that enables use of 1, 2, or 4 outputs for full resolution readout of 138 frames per second. a vertical overflow drain structure suppresses image blooming and enables electronic shuttering for precise exposure control. table 1. general specifications parameter typical value architecture interline ccd, progressive scan total number of pixels 1364 (h) 760 (v) number of effective pixels 1320 (h) 736 (v) number of active pixels 1280 (h) 720 (v) pixel size 5.5 m (h) 5.5 m (v) active image size 7.04 mm (h) 3.96 mm (v) 8.08 mm (diag.), 1/2 optical format aspect ratio 16:9 number of outputs 1, 2, or 4 charge capacity 20,000 electrons output sensitivity 34 v/e ? quantum efficiency pan ( ? aba, ? qba, ? pba) r, g, b ( ? fba, ? qba) r, g, b ( ? cba, ? pba) 44% 31%, 37%, 38% 29%, 37%, 39% base iso kai ? 01150 ? aba kai ? 01150 ? fba kai ? 01150 ? cba kai ? 01150 ? pba 330 170 150 330 read noise (f = 40 mhz) 12 e ? rms dark current photodiode / vccd 7 / 140 e ? /s dark current doubling temp photodiode / vccd 7 c / 9 c dynamic range 64 db charge transfer efficiency 0.999999 blooming suppression > 300 x smear ? 100 db image lag < 10 electrons maximum pixel clock speed 40 mhz maximum frame rate quad / dual / single output 138 / 69 / 36 fps package options 68 pin pga 64 pin clcc cover glass ar coated, 2-sides or clear glass note: all parameters are specified at t = 40 c unless otherwise noted. features ? bayer color pattern, truesense sparse color filter pattern, and monochrome configurations ? progressive scan readout ? flexible readout architecture ? high frame rate ? high sensitivity ? low noise architecture ? excellent smear performance ? package pin reserved for device identification applications ? intelligent traffic systems ? security / surveillance ? industrial imaging www.onsemi.com figure 1. kai ? 01150 interline ccd image sensor see detailed ordering and shipping information on page 2 of this data sheet. ordering information
kai ? 01150 www.onsemi.com 2 the sensor is available with the truesense sparse color filter pattern, a technology which provides a 2x improvement in light sensitivity compared to a standard color bayer part. the sensor shares common pga pin ? out and electrical configurations with other devices based on the truesense 5.5 micron interline transfer ccd platform, allowing a single camera design to support multiple members of this sensor family. ordering information standard devices see full datasheet for ordering information associated with devices no longer recommended for new designs. table 2. ordering information ? standard devices part number description marking code kai ? 01150 ? aba ? jd ? ba monochrome, telecentric microlens, pga package, sealed clear cover glass with ar coating (both sides), standard grade kai ? 01150 ? aba serial number kai ? 01150 ? aba ? jd ? ae monochrome, telecentric microlens, pga package, sealed clear cover glass with ar coating (both sides), engineering grade kai ? 01150 ? aba ? fd ? ba monochrome, telecentric microlens, clcc package, sealed clear cover glass with ar coating (both sides), standard grade kai ? 01150 ? aba ? fd ? ae monochrome, telecentric microlens, clcc package, sealed clear cover glass with ar coating (both sides), engineering grade kai ? 01150 ? fba ? jd ? ba gen2 color (bayer rgb), telecentric microlens, pga package, sealed clear cover glass with ar coating (both sides), standard grade kai ? 01150 ? fba serial number kai ? 01150 ? fba ? jd ? ae gen2 color (bayer rgb), telecentric microlens, pga package, sealed clear cover glass with ar coating (both sides), engineering grade kai ? 01150 ? fba ? fd ? ba gen2 color (bayer rgb), telecentric microlens, clcc package, sealed clear cover glass with ar coating (both sides), standard grade kai ? 01150 ? fba ? fd ? ae gen2 color (bayer rgb), telecentric microlens, clcc package, sealed clear cover glass with ar coating (both sides), engineering grade kai ? 01150 ? fba ? jb ? b2 gen2 color (bayer rgb), telecentric microlens, pga package, sealed clear cover glass (no coatings), grade 2 kai ? 01150 ? fba ? jb ? ae gen2 color (bayer rgb), telecentric microlens, pga package, sealed clear cover glass (no coatings), engineering grade kai ? 01150 ? qba ? jd ? ba gen2 color (truesense sparse cfa), telecentric microlens, pga package, sealed clear cover glass with ar coating (both sides), standard grade kai ? 01150 ? qba serial number kai ? 01150 ? qba ? jd ? ae gen2 color (truesense sparse cfa), telecentric microlens, pga package, sealed clear cover glass with ar coating (both sides), engineering grade kai ? 01150 ? qba ? fd ? ba gen2 color (truesense sparse cfa), telecentric microlens, clcc package, sealed clear cover glass with ar coating (both sides), standard grade kai ? 01150 ? qba ? fd ? ae gen2 color (truesense sparse cfa), telecentric microlens, clcc package, sealed clear cover glass with ar coating (both sides), engineering grade see the on semiconductor device nomenclature document (tnd310/d) for a full description of the naming convention used for image sensors. for reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com .
kai ? 01150 www.onsemi.com 3 not recommended for new designs table 3. ordering information ? not recommended for new designs part number description marking code kai ? 01150 ? cba ? jd ? ba gen1 color (bayer rgb), telecentric microlens, pga package, sealed clear cover glass with ar coating (both sides), standard grade kai ? 01150 ? cba serial number kai ? 01150 ? cba ? jd ? ae gen1 color (bayer rgb), telecentric microlens, pga package, sealed clear cover glass with ar coating (both sides), engineering grade kai ? 01150 ? cba ? fd ? ba gen1 color (bayer rgb), telecentric microlens, clcc package, sealed clear cover glass with ar coating (both sides), standard grade kai ? 01150 ? cba ? fd ? ae gen1 color (bayer rgb), telecentric microlens, clcc package, sealed clear cover glass with ar coating (both sides), engineering grade kai ? 01150 ? cba ? jb ? b2 gen1 color (bayer rgb), telecentric microlens, pga package, sealed clear cover glass (no coatings), grade 2 kai ? 01150 ? cba ? jb ? ae gen1 color (bayer rgb), telecentric microlens, pga package, sealed clear cover glass (no coatings), engineering grade kai ? 01150 ? pba ? jd ? ba gen1 color (truesense sparse cfa), telecentric microlens, pga package, sealed clear cover glass with ar coating (both sides), standard grade kai ? 01150 ? pba serial number kai ? 01150 ? pba ? jd ? ae gen1 color (truesense sparse cfa), telecentric microlens, pga package, sealed clear cover glass with ar coating (both sides), engineering grade kai ? 01150 ? pba ? fd ? ba gen1 color (truesense sparse cfa), telecentric microlens, clcc package, sealed clear cover glass with ar coating (both sides), standard grade kai ? 01150 ? pba ? fd ? ae gen1 color (truesense sparse cfa), telecentric microlens, clcc package, sealed clear cover glass with ar coating (both sides), engineering grade
kai ? 01150 www.onsemi.com 4 device description architecture figure 2. block diagram 22 12 dark 12 20 v1b 8 buffer 20 8 22 1 dummy 640 640 640 640 v2b v3b v4b v1t v2t v3t v4t h1sa h1ba h2sa h2ba rda ra vdda vouta gnd h1sb h1bb h2sb h2bb rdc rc vddc voutc gnd rdd rd vddd voutd gnd rdb rb vddb voutb gnd v1b v2b v3b v4b v1t v2t v3t v4t h1sd h1bd h2sd h2bd h1sc h1bc h2sc h2bc h2sla oga h2slc ogc h2sld ogd h2slb ogb esd esd sub sub 1 22 20 10 1 22 20 10 1 22 20 10 1 22 20 10 devid 1280 (h) 720 (v) 5.5 m 5.5 m pixels (last vccd phase = v1 h1s) dark reference pixels there are 12 dark reference rows at the top and 12 dark rows at the bottom of the image sensor. the dark rows are not entirely dark and so should not be used for a dark reference level. use the 22 dark columns on the left or right side of the image sensor as a dark reference. under normal circumstances use only the center 20 columns of the 22 column dark reference due to potential light leakage. dummy pixels within each horizontal shift register there are 11 leading additional shift phases. these pixels are designated as dummy pixels and should not be used to determine a dark reference level. in addition, there is one dummy row of pixels at the top and bottom of the image. active buffer pixels 20 unshielded pixels adjacent to any leading or trailing dark reference regions are classified as active buffer pixels. these pixels are light sensitive but are not tested for defects and non-uniformities. image acquisition an electronic representation of an image is formed when incident photons falling on the sensor plane create electron-hole pairs within the individual silicon photodiodes. these photoelectrons are collected locally by the formation of potential wells at each photosite. below photodiode saturation, the number of photoelectrons collected at each pixel is linearly dependent upon light level and exposure time and non-linearly dependent on wavelength. when the photodiodes charge capacity is reached, excess electrons are discharged into the substrate to prevent blooming. esd protection adherence to the power-up and power-down sequence is critical. failure to follow the proper power-up and power-down sequences may cause damage to the sensor. see power-up and power-down sequence section.
kai ? 01150 www.onsemi.com 5 bayer color filter pattern figure 3. bayer color filter pattern 22 12 dark 12 20 v1b 8 buffer 20 8 22 1 dummy 640 640 640 640 v2b v3b v4b v1t v2t v3t v4t h1sa h1ba h2sa h2ba rda ra vdda vouta gnd h1sb h1bb h2sb h2bb rdc rc vddc voutc gnd rdd rd vddd voutd gnd rdb rb vddb voutb gnd v1b v2b v3b v4b v1t v2t v3t v4t h1sd h1bd h2sd h2bd h1sc h1bc h2sc h2bc h2sla oga h2slc ogc h2sld ogd h2slb ogb esd esd sub sub 1 22 20 10 1 22 20 10 1 22 20 10 1 22 20 10 devid 1280 (h) 720 (v) 5.5 m 5.5 m pixels (last vccd phase = v1 h1s) g b g r g b g r g b g r g b g r truesense sparse color filter pattern figure 4. truesense sparse color filter pattern 22 12 dark 12 20 v1b 8 buffer 20 8 22 1 dummy 640 640 640 640 v2b v3b v4b v1t v2t v3t v4t h1sa h1ba h2sa h2ba rda ra vdda vouta gnd h1sb h1bb h2sb h2bb rdc rc vddc voutc gnd rdd rd vddd voutd gnd rdb rb vddb voutb gnd v1b v2b v3b v4b v1t v2t v3t v4t h1sd h1bd h2sd h2bd h1sc h1bc h2sc h2bc h2sla oga h2slc ogc h2sld ogd h2slb ogb esd esd sub sub 1 22 20 10 1 22 20 10 1 22 20 10 1 22 20 10 devid 1280 (h) 720 (v) 5.5 m 5.5 m pixels (last vccd phase = v1 h1s) p g p g p r p r p b p b p g p g p g p g p r p r p b p b p g p g p g p g p r p r p b p b p g p g p g p g p r p r p b p b p g p g
kai ? 01150 www.onsemi.com 6 physical description pga pin description and device orientation figure 5. pga package pin designations ? top view pixel (1, 1) 1 3 5 7 9 11 13 15 17 19 21 v3b v1b v4b vdda v2b gnd vouta ra rda h2sla oga h1bb h2bb h2sb h1sb n/c sub h2sa h1sa h1ba h2ba 23 h2slb ogb 25 27 29 31 v1b v4b vddb v2b gnd voutb rb rdb 33 v3b esd 65 63 61 59 57 55 53 51 49 47 esd v4t v1t v2t vddc voutc gnd rdc rc ogc h2slc h2bd h1bd h1sd h2sd sub n/c h1sc h2sc h2bc h1bc 45 ogd h2sld 43 41 39 37 v4t v1t v2t vddd voutd gnd rdd rd 35 devid v3t 67 v3t 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 4 6 10 12 14 16 18 20 22 24 26 30 32 34 8 28 table 4. pga package pin description pin name description 1 v3b vertical ccd clock, phase 3, bottom 3 v1b vertical ccd clock, phase 1, bottom 4 v4b vertical ccd clock, phase 4, bottom 5 vdda output amplifier supply, quadrant a 6 v2b vertical ccd clock, phase 2, bottom 7 gnd ground 8 vouta video output, quadrant a 9 ra reset gate, quadrant a 10 rda reset drain, quadrant a 11 h2sla horizontal ccd clock, phase 2, storage, last phase, quadrant a 12 oga output gate, quadrant a 13 h1ba horizontal ccd clock, phase 1, barrier, quadrant a 14 h2ba horizontal ccd clock, phase 2, barrier, quadrant a 15 h2sa horizontal ccd clock, phase 2, storage, quadrant a 16 h1sa horizontal ccd clock, phase 1, storage, quadrant a 17 n/c no connect 18 sub substrate 19 h2sb horizontal ccd clock, phase 2, storage, quadrant b 20 h1sb horizontal ccd clock, phase 1, storage, quadrant b 21 h1bb horizontal ccd clock, phase 1, barrier, quadrant b 22 h2bb horizontal ccd clock, phase 2, barrier, quadrant b 23 h2slb horizontal ccd clock, phase 1, storage, last phase, quadrant b 24 ogb output gate, quadrant b
kai ? 01150 www.onsemi.com 7 table 4. pga package pin description (continued) pin description name 25 rb reset gate, quadrant b 26 rdb reset drain, quadrant b 27 gnd ground 28 voutb video output, quadrant b 29 vddb output amplifier supply, quadrant b 30 v2b vertical ccd clock, phase 2, bottom 31 v1b vertical ccd clock, phase 1, bottom 32 v4b vertical ccd clock, phase 4, bottom 33 v3b vertical ccd clock, phase 3, bottom 34 esd esd protection disable 35 v3t vertical ccd clock, phase 3, top 36 devid device identification 37 v1t vertical ccd clock, phase 1, top 38 v4t vertical ccd clock, phase 4, top 39 vddd output amplifier supply, quadrant d 40 v2t vertical ccd clock, phase 2, top 41 gnd ground 42 voutd video output, quadrant d 43 rd reset gate, quadrant d 44 rdd reset drain, quadrant d 45 h2sld horizontal ccd clock, phase 2, storage, last phase, quadrant d 46 ogd output gate, quadrant d 47 h1bd horizontal ccd clock, phase 1, barrier, quadrant d 48 h2bd horizontal ccd clock, phase 2, barrier, quadrant d 49 h2sd horizontal ccd clock, phase 2, storage, quadrant d 50 h1sd horizontal ccd clock, phase 1, storage, quadrant d 51 n/c no connect 52 sub substrate 53 h2sc horizontal ccd clock, phase 2, storage, quadrant c 54 h1sc horizontal ccd clock, phase 1, storage, quadrant c 55 h1bc horizontal ccd clock, phase 1, barrier, quadrant c 56 h2bc horizontal ccd clock, phase 2, barrier, quadrant c 57 h2slc horizontal ccd clock, phase 2, storage, last phase, quadrant c 58 ogc output gate, quadrant c 59 rc reset gate, quadrant c 60 rdc reset drain, quadrant c 61 gnd ground 62 voutc video output, quadrant c 63 vddc output amplifier supply, quadrant c 64 v2t vertical ccd clock, phase 2, top 65 v1t vertical ccd clock, phase 1, top 66 v4t vertical ccd clock, phase 4, top 67 v3t vertical ccd clock, phase 3, top 68 esd eds protection disable 1. liked named pins are internally connected and should have a common drive signal. 2. n/c pins (17, 51) should be left floating.
kai ? 01150 www.onsemi.com 8 ceramic leadless chip carrier pin description figure 6. clcc package pin designations ? top view 116 17 64 32 33 48 49 8 24 40 56 rda ra oga h2ba h1ba h1sa h2sa sub h2sb h1sb h1bb h2bb h2slb ogb rb rdb gnd voutb vddb v2b v1b v4b v3b devid v3t v4t v1t v2t vddd voutd gnd rdd rd ogd h2sld h2bd h1bd h1sd sub h2sd h1sc h1bc h2bc h2slc h2sc ogc rc rdc gnd voutc vddc v2t v1t v4t v3t esd v3b v4b v1b v2b vdda vouta gnd 2 34567 9 18 19 20 21 22 23 25 26 27 28 29 30 31 34 35 36 37 38 39 41 42 43 44 45 46 47 50 51 52 53 54 55 57 58 59 60 61 62 63 10 11 12 13 14 15 h2sla pixel (1, 1) table 5. clcc package pin description pin name description 1 rda reset drain, quadrant a 2 ra reset gate, quadrant a 3 oga output gate, quadrant a 4 h2sla horizontal ccd clock, phase 2, storage, last phase, quadrant a 5 h2ba horizontal ccd clock, phase 2, barrier, quadrant a 6 h1ba horizontal ccd clock, phase 1, barrier, quadrant a 7 h1sa horizontal ccd clock, phase 1, storage, quadrant a 8 h2sa horizontal ccd clock, phase 2, storage, quadrant a 9 sub substrate 10 h2sb horizontal ccd clock, phase 2, storage, quadrant b 11 h1sb horizontal ccd clock, phase 1, storage, quadrant b 12 h1bb horizontal ccd clock, phase 1, barrier, quadrant b 13 h2bb horizontal ccd clock, phase 2, barrier, quadrant b 14 h2slb horizontal ccd clock, phase 2, storage, last phase, quadrant b 15 ogb output gate, quadrant b 16 rb reset gate, quadrant b 17 rdb reset drain, quadrant b 18 gnd ground 19 voutb video output, quadrant b
kai ? 01150 www.onsemi.com 9 table 5. clcc package pin description (continued) pin description name 20 vddb output amplifier supply, quadrant b 21 v2b vertical ccd clock, phase 2, bottom 22 v1b vertical ccd clock, phase 1, bottom 23 v4b vertical ccd clock, phase 4, bottom 24 v3b vertical ccd clock, phase 3, bottom 25 devid device identification 26 v3t vertical ccd clock, phase 3, top 27 v4t vertical ccd clock, phase 4, top 28 v1t vertical ccd clock, phase 1, top 29 v2t vertical ccd clock, phase 2, top 30 vddd output amplifier supply, quadrant d 31 voutd video output, quadrant d 32 gnd ground 33 rdd reset drain, quadrant d 34 rd reset gate, quadrant d 35 ogd output gate, quadrant d 36 h2sld horizontal ccd clock, phase 2, storage, last phase, quadrant d 37 h2bd horizontal ccd clock, phase 2, barrier, quadrant d 38 h1bd horizontal ccd clock, phase 1, barrier, quadrant d 39 h1sd horizontal ccd clock, phase 1, storage, quadrant d 40 h2sd horizontal ccd clock, phase 2, storage, quadrant d 41 sub substrate 42 h2sc horizontal ccd clock, phase 2, storage, quadrant c 43 h1sc horizontal ccd clock, phase 1, storage, quadrant c 44 h1bc horizontal ccd clock, phase 1, barrier, quadrant c 45 h2bc horizontal ccd clock, phase 2, barrier, quadrant c 46 h2slc horizontal ccd clock, phase 2, storage, last phase, quadrant c 47 ogc output gate, quadrant c 48 rc reset gate, quadrant c 49 rdc reset drain, quadrant c 50 gnd ground 51 voutc video output, quadrant c 52 vddc output amplifier supply, quadrant c 53 v2t vertical ccd clock, phase 2, top 54 v1t vertical ccd clock, phase 1, top 55 v4t vertical ccd clock, phase 4, top 56 v3t vertical ccd clock, phase 3, top 57 esd esd protection disable 58 v3b vertical ccd clock, phase 3, bottom 59 v4b vertical ccd clock, phase 4, bottom 60 v1b vertical ccd clock, phase 1, bottom 61 v2b vertical ccd clock, phase 2, bottom 62 vdda output amplifier supply, quadrant a 63 vouta video output, quadrant a 64 gnd ground 1. liked named pins are internally connected and should have a common drive signal.
kai ? 01150 www.onsemi.com 10 imaging performance table 6. typical operation conditions unless otherwise noted, the imaging performance specifications are measured using the following conditions. description condition notes light source continuous red, green and blue led illumination for monochrome sensor, only green led used. operation nominal operating voltages and timing table 7. specifications description symbol min. nom. max. units sampling plan temperature tested at ( c) notes dark field global non ? uniformity dsnu ? ? 2.0 mvpp die 27, 40 bright field global non ? uniformity ? 2.0 5.0 %rms die 27, 40 1 bright field global peak to peak non ? uniformity prnu ? 5.0 15.0 %pp die 27, 40 1 bright field center non ? uniformity ? 1.0 2.0 %rms die 27, 40 1 maximum photoresponse nonlinearity nl ? 2 ? % design 2 maximum gain difference between outputs g ? 10 ? % design 2 maximum signal error due to nonlinearity differences nl ? 1 ? % design 2 horizontal ccd charge capacity hne ? 55 ? ke ? design vertical ccd charge capacity vne ? 45 ? ke ? design photodiode charge capacity pne ? 20 ? ke ? die 27, 40 3 horizontal ccd charge transfer efficiency hcte 0.999995 0.999999 ? die vertical ccd charge transfer efficiency vcte 0.999995 0.999999 ? die photodiode dark current ipd ? 7 70 e/p/s die 40 vertical ccd dark current ivd ? 140 400 e/p/s die 40 image lag lag ? ? 10 e ? design antiblooming factor xab 300 ? ? design vertical smear smr ? ? 100 ? db design read noise n e ? t ? 12 ? e ? rms design 4 dynamic range dr ? 64 ? db design 4, 5 output amplifier dc offset v odc ? 9.4 ? v die 27, 40 output amplifier bandwidth f ? 3db ? 250 ? mhz die 6 output amplifier impedance r out ? 127 ? die 27, 40 output amplifier sensitivity v/ n ? 34 ? v/e ? design 1. per color 2. value is over the range of 10% to 90% of photodiode saturation. 3. the operating value of the substrate voltage, vab, will be marked on the shipping container for each device. the value of vab is set such that the photodiode charge capacity is 680 mv. 4. at 40 mhz 5. uses 20log (pne/ n e ? t ) 6. assumes 5 pf load.
kai ? 01150 www.onsemi.com 11 table 8. kai ? 01150 ? aba and kai ? 01150 ? pba configurations description symbol min. nom. max. units sampling plan temperature tested at ( c) notes peak quantum efficiency qe max ? 44 ? % design peak quantum efficiency wavelength qe ? 480 ? nm design table 9. kai ? 01150 ? fba and kai ? 01150 ? qba gen2 color configurations with mar glass description symbol min. nom. max. units sampling plan temperature tested at ( c) notes peak quantum efficiency blue green red qe max ? 38 37 31 ? % design peak quantum efficiency wavelength blue green red qe ? 460 530 605 ? nm design table 10. kai ? 01150 ? cba and kai ? 01150 ? pba gen1 color configurations with mar glass description symbol min. nom. max. units sampling plan temperature tested at ( c) notes peak quantum efficiency blue green red qe max ? 39 37 29 ? % design 1 peak quantum efficiency wavelength blue green red qe ? 470 540 620 ? nm design 1 1. this color filter set configuration (gen1) is not recommended for new designs. table 11. kai ? 01150 ? fba gen2 color configurations with clear glass description symbol min. nom. max. units sampling plan temperature tested at ( c) notes peak quantum efficiency blue green red qe max ? 35 34 29 ? % design peak quantum efficiency wavelength blue green red qe ? 460 530 605 ? nm design table 12. kai ? 01150 ? cba gen1 color configurations with clear glass description symbol min. nom. max. units sampling plan temperature tested at ( c) notes peak quantum efficiency blue green red qe max ? 36 34 27 ? % design 1 peak quantum efficiency wavelength blue green red qe ? 470 540 620 ? nm design 1 1. this color filter set configuration (gen1) is not recommended for new designs.
kai ? 01150 www.onsemi.com 12 typical performance curves quantum efficiency monochrome with microlens figure 7. monochrome with microlens quantum efficiency note: the pga and clcc versions have different quantum efficiencies due to differences in the cover glass transmission. see figure 34: cover glass transmission for more details. color (bayer rgb) with microlens and mar cover glass (gen2 and gen1 cfa) figure 8. mar glass color (bayer) with microlens quantum efficiency
kai ? 01150 www.onsemi.com 13 color (bayer rgb) with microlens and clear cover glass (gen2 and gen1 cfa) figure 9. clear glass color (bayer) with microlens quantum efficiency color (truesense sparse cfa) with microlens (gen2 and gen1 cfa) figure 10. color (truesense sparse cfa) with microlens quantum efficiency
kai ? 01150 www.onsemi.com 14 angular quantum efficiency for the curves marked ?horizontal?, the incident light angle is varied in a plane parallel to the hccd. for the curves marked ?vertical?, the incident light angle is varied in a plane parallel to the vccd. monochrome with microlens figure 11. monochrome with microlens angular quantum efficiency 0 10 20 30 40 50 60 70 80 90 100 ? 30 ? 20 ? 10 0 10 20 30 angle (degrees) relative quantum efficiency (%) vertical horizontal dark current vs. temperature figure 12. dark current vs. temperature 0.1 1 10 100 1000 10000 2.9 3.0 3.1 3.2 3.3 3.4 dark current (e/s) 1000/t (k) vccd photodiode 60 50 40 30 21 72 t ( c)
kai ? 01150 www.onsemi.com 15 power-estimated figure 13. power 0.0 0.1 0.2 0.3 0.4 0.5 0.6 10 15 20 25 30 35 40 power (w) hccd frequency (mhz) single dual quad frame rates figure 14. frame rates 0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 100 120 140 160 180 200 10 15 20 25 30 35 40 frame rate (fps) hccd frequency (mhz) single dual (left/right) quad
kai ? 01150 www.onsemi.com 16 defect definitions table 13. operation conditions for defect testing at 40 c description condition notes operational mode two outputs, using vouta and voutc, continuous readout hccd clock frequency 10 mhz pixels per line 1520 1 lines per frame 480 2 line time 154.9 s frame time 74.4 ms photodiode integration time mode a: pd_tint = frame time = 74.4 ms, no electronic shutter used mode b: pd_tint = 33 ms, electronic shutter used vccd integration time 58.9 ms 3 temperature 40 c light source continuous red, green and blue led illumination 4 operation nominal operating voltages and timing 1. horizontal overclocking used. 2. vertical overclocking used. 3. vccd integration time = 380 lines line time, which is the total time a pixel will spend in the vccd registers. 4. for monochrome sensor, only the green led is used. table 14. defect definitions for testing at 40 c description definition standard grade grade 2 notes major dark field defective bright pixel pd_tint = mode a defect 25 mv or pd_tint = mode b defect 12 mv 10 10 1 major bright field defective dark pixel defect 12% 10 10 1 minor dark field defective bright pixel pd_tint = mode a defect 13 mv or pd_tint = mode b defect 6 mv 100 100 cluster defect (standard grade) a group of 2 to 10 contiguous major defective pixels, but no more than 2 adjacent defects horizontally. 0 n/a 2 cluster defect (grade 2) a group of 2 to 10 contiguous major defective pixels. n/a 5 2 column defect a group of more than 10 contiguous major defective pixels along a single column. 0 0 2 1. for the color device (kai ? 01150 ? cba or kai ? 01150 ? pba), a brig ht field defective pixel deviates by 12% with respect to pixels of the same color. 2. column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects ).
kai ? 01150 www.onsemi.com 17 table 15. operation conditions for defect testing at 27 c description condition notes operational mode two outputs, using vouta and voutc, continuous readout hccd clock frequency 20 mhz pixels per line 1520 1 lines per frame 480 2 line time 77.8 s frame time 37.3 ms photodiode integration time (pd_tint) mode a: pd_tint = frame time = 37.3 ms, no electronic shutter used mode b: pd_tint = 33 ms, electronic shutter used vccd integration time 29.5 ms 3 temperature 27 c light source continuous red, green and blue led illumination 4 operation nominal operating voltages and timing 1. horizontal overclocking used. 2. vertical overclocking used. 3. vccd integration time = 380 lines line time, which is the total time a pixel will spend in the vccd registers. 4. for monochrome sensor, only the green led is used. table 16. defect definitions for testing at 27 c description definition standard grade grade 2 notes major dark field defective bright pixel pd_tint = mode a defect 8 mv or pd_tint = mode b defect 4 mv 10 10 1 major bright field defective dark pixel defect 12% 10 10 1 cluster defect (standard grade) a group of 2 to 10 contiguous major defective pixels, but no more than 2 adjacent defects horizontally. 0 n/a 2 cluster defect (grade 2) a group of 2 to 10 contiguous major defective pixels. n/a 5 2 column defect a group of more than 10 contiguous major defective pixels along a single column. 0 0 2 1. for the color device (kai ? 01150 ? cba or kai ? 01150 ? pba), a brig ht field defective pixel deviates by 12% with respect to pixels of the same color. 2. column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects ). defect map the defect map supplied with each sensor is based upon testing at an ambient (27 c) temperature. minor point defects are not included in the defect map. all defective pixels are reference to pixel 1, 1 in the defect maps. see figure 15: regions of interest for the location of pixel 1, 1.
kai ? 01150 www.onsemi.com 18 test definitions test regions of interest image area roi: pixel (1, 1) to pixel (1320, 736) active area roi: pixel (21, 9) to pixel (1300, 728) center roi: pixel (611, 319) to pixel (710, 418) only the active area roi pixels are used for performance and defect tests. overclocking the test system timing is configured such that the sensor is overclocked in both the vertical and horizontal directions. see figure 15 for a pictorial representation of the regions of interest. figure 15. regions of interest horizontal overclock vouta 1, 1 21, 9 pixel pixel voutc 12 dark rows 22 dark columns 8 buffer rows 20 buffer columns 20 buffer columns 22 dark columns 1280 x 720 active pixels 12 dark rows 8 buffer rows tests dark field global non-uniformity this test is performed under dark field conditions. the sensor is partitioned into 60 sub regions of interest, each of which is 128 by 120 pixels in size. see figure 16: test sub regions of interest. the average signal level of each of the 60 sub regions of interest is calculated. the signal level of each of the sub regions of interest is calculated using the following formula: signal of roi[i] (roi average in counts units : mvpp (millivolts peak to peak) horizontal overclock average in counts) mv per count where i = 1 to 144. during this calculation on the 60 sub regions of interest, the maximum and minimum signal levels are found. the dark field global uniformity is then calculated as the maximum signal found minus the minimum signal level found. global non-uniformity this test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 476 mv). prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 680 mv. global non-uniformity is defined as global non ? uniformity 100 active area standard deviation active area signal active area signal = active area average ? dark column average units : % rms global peak to peak non-uniformity this test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 476 mv). prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 680 mv. the sensor is partitioned into 60 sub regions of interest, each of which is 128 by 120 pixels in size. see figure 16: test sub regions of interest. the average signal level of each of the 60 sub regions of interest (roi) is calculated. the signal level of each of the sub regions of interest is calculated using the following formula: signal of roi[i] (roi average in counts horizontal overclock average in counts) mv per count
kai ? 01150 www.onsemi.com 19 where i = 1 to 60. during this calculation on the 60 sub regions of interest, the maximum and minimum signal levels are found. the global peak to peak uniformity is then calculated as: global uniformity 100 max. signal min. signal active area signal units : % pp center non-uniformity this test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 476 mv). prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 680 mv. defects are excluded for the calculation of this test. this test is performed on the center 100 by 100 pixels of the sensor. center uniformity is defined as: center roi uniformity 100 center roi standard deviation center roi signal center roi signal = center roi average ? dark colum average units : % rms dark field defect test this test is performed under dark field conditions. the sensor is partitioned into 60 sub regions of interest, each of which is 128 by 120 pixels in size. in each region of interest, the median value of all pixels is found. for each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the defect threshold specified in the ?defect definitions? section. bright field defect test this test is performed with the imager illuminated to a level such that the output is at approximately 476 mv. prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 680 mv. the average signal level of all active pixels is found. the bright and dark thresholds are set as: dark defect threshold = active area signal threshold bright defect threshold = active area signal threshold the sensor is then partitioned into 60 sub regions of interest, each of which is 128 by 120 pixels in size. in each region of interest, the average value of all pixels is found. for each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the bright threshold specified or if it is less than or equal to the median value of that region of interest minus the dark threshold specified. example for major bright field defective pixels: ? average value of all active pixels is found to be 476 mv. ? dark defect threshold: 476 mv ? 12 % = 57 mv. ? bright defect threshold: 476 mv ? 12 % = 57 mv. ? region of interest #1 selected. this region of interest is pixels 21, 9 to pixels 148, 128. ? median of this region of interest is found to be 470 mv. ? any pixel in this region of interest that is (470 + 57 mv) 527 mv in intensity will be marked defective. ? any pixel in this region of interest that is (470 ? 57 mv) 413 mv in intensity will be marked defective. ? all remaining 60 sub regions of interest are analyzed for defective pixels in the same manner. test sub regions of interest figure 16. test sub regions of interest pixel (21,9) pixel (1300,728) vouta 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
kai ? 01150 www.onsemi.com 20 operation absolute maximum ratings absolute maximum rating is defined as a level or condition that should not be exceeded at any time per the description. if the level or the condition is exceeded, the device will be degraded and may be damaged. operation at these values will reduce mttf. table 17. absolute maximum ratings description symbol minimum maximum unit notes operating temperature t op ? 50 70 c 1 humidity rh 5 90 % 2 output bias current i out ? 60 ma 3 off-chip load c l ? 10 pf stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. noise performance will degrade at higher temperatures. 2. t = 25 c. excessive humidity will degrade mttf. 3. total for all outputs. maximum current is ? 15 ma for each output. avoid shorting output pins to ground or any low impedance source during operation. amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivi ty). table 18. absolute maximum voltage ratings between pins and ground description minimum maximum unit notes vdd , vout ? 0.4 17.5 v 1 rd ? 0.4 15.5 v 1 v1b, v1t esd ? 0.4 esd + 24.0 v v2b, v2t, v3b, v3t, v4b, v4t esd ? 0.4 esd + 14.0 v h1s , h1b , h2s , h2b , h2sl , r , og esd ? 0.4 esd + 14.0 v 1 esd ? 10.0 0.0 v sub ? 0.4 40.0 v 2 1. denotes a, b, c or d. 2. refer to application note using interline ccd image sensors in high intensity visible lighting conditions
kai ? 01150 www.onsemi.com 21 power-up and power-down sequenc e adherence to the power-up and power-down sequence is critical. failure to follow the proper power-up and power-down sequences may cause damage to the sensor. figure 17. power-up and power-down sequence vdd sub esd vccd low hccd low time v+ v ? do not pulse the electronic shutter until esd is stable activate all other biases when esd is stable and sub is above 3 v 1. activate all other biases when esd is stable and sub is above 3 v. 2. do not pulse the electronic shutter until esd is stable. 3. vdd cannot be +15 v when sub is 0 v. 4. the image sensor can be protected from an accidental improper esd voltage by current limiting the sub current to less than 10 ma. sub and vdd must always be greater than gnd. esd must always be less than gnd. placing diodes between sub, vdd, esd and ground will protect the sensor from accidental overshoots of sub, vdd and esd during power on and power off. see the figure below. notes: the vccd clock waveform must not have a negative overshoot more than 0.4 v below the esd voltage. figure 18. vccd clock waveform all vccd clock absolute maximum overshoot of 0.4 v 0.0 v esd esd ? 0.4 v example of external diode protection for sub, vdd and esd. denotes a, b, c or d. figure 19. example of external diode protection esd gnd vdd sub
kai ? 01150 www.onsemi.com 22 dc bias operating conditions table 19. dc bias operating conditions description pins symbol min. nom. max. unit max. dc current notes reset drain rd rd 11.8 12.0 12.2 v 10 a 1 output gate og og ? 2.2 ? 2.0 ? 1.8 v 10 a 1 output amplifier supply vdd v dd 14.5 15.0 15.5 v 11.0 ma 1, 2 ground gnd gnd 0.0 0.0 0.0 v ? 1.0 ma substrate sub v sub 5.0 v ab v dd v 50 a 3, 8 esd protection disable esd esd ? 9.5 ? 9.0 vx_l v 50 a 6, 7, 9 output bias current vout i out ? 3.0 ? 7.0 ? 10.0 ma ? 1, 4, 5 1. denotes a, b, c or d. 2. the maximum dc current is for one output. i dd = i out + i ss . see figure 20. 3. the operating value of the substrate voltage, v ab , will be marked on the shipping container for each device. the value of v ab is set such that the photodiode charge capacity is the nominal p ne (see specifications). 4. an output load sink must be applied to each vout pin to activate each output amplifier. 5. nominal value required for 40 mhz operation per output. may be reduced for slower data rates and lower noise. 6. adherence to the power-up and power-down sequence is critical. see power up and power down sequence section. 7. esd maximum value must be less than or equal to v1_l + 0.4 v and v2_l + 0.4 v. 8. refer to application note using interline ccd image sensors in high intensity visible lighting conditions. 9. where vx_l is the level set for v1_l, v2_l, v3_l, or v4_l in the application. figure 20. output amplifier source follower #1 source follower #2 source follower #3 floating diffusion i ss i dd i out vout vdd r rd hccd og
kai ? 01150 www.onsemi.com 23 ac operating conditions table 20. clock levels description pins (note 1) symbol level min. nom. max. unit capacitance (note 2) vertical ccd clock, phase 1 v1b, v1t v1_l low ? 8.2 ? 8.0 ? 7.8 v 6 nf (note 6) v1_m mid ? 0.2 0.0 0.2 v1_h high 11.5 12.0 12.5 vertical ccd clock, phase 2 v2b, v2t v2_l low ? 8.2 ? 8.0 ? 7.8 v 6 nf (note 6) v2_h high ? 0.2 0.0 0.2 vertical ccd clock, phase 3 v3b, v3t v3_l low ? 8.2 ? 8.0 ? 7.8 v 6 nf (note 6) v3_h high ? 0.2 0.0 0.2 vertical ccd clock, phase 4 v4b, v4t v4_l low ? 8.2 ? 8.0 ? 7.8 v 6 nf (note 6) v4_h high ? 0.2 0.0 0.2 horizontal ccd clock, phase 1 storage h1s h1s_l low ? 5.2 (note 7) ? 4.0 ? 3.8 v 90 pf (note 6) h1s_a amplitude 3.8 4.0 5.2 (note 7) horizontal ccd clock, phase 1 barrier h1b h1b_l low ? 5.2 (note 7) ? 4.0 ? 3.8 v 60 pf (note 6) h1b_a amplitude 3.8 4.0 5.2 (note 7) horizontal ccd clock, phase 2 storage h2s h2s_l low ? 5.2 (note 7) ? 4.0 ? 3.8 v 90 pf (note 6) h2s_a amplitude 3.8 4.0 5.2 (note 7) horizontal ccd clock, phase 2 barrier h2b h2b_l low ? 5.2 (note 7) ? 4.0 ? 3.8 v 60 pf (note 6) h2b_a amplitude 3.8 4.0 5.2 (note 7) horizontal ccd clock, last phase (note 3) h2sl h2sl_l low ? 5.2 ? 5.0 ? 4.8 v 20 pf (note 6) h2sl_a amplitude 4.8 5.0 5.2 reset gate r r_l (note 4) low ? 3.5 ? 2.0 ? 1.5 v 16 pf (note 6) r_h high 2.5 3.0 4.0 electronic shutter (note 5) sub ves high 29.0 30.0 40.0 v 400 pf (note 6) 1. denotes a, b, c or d. 2. capacitance is total for all like named pins. 3. use separate clock driver for improved speed performance. 4. reset low should be set to ?3 v for signal levels greater than 40,000 electrons. 5. refer to application note using interline ccd image sensors in high intensity visible lighting conditions. 6. capacitance values are estimated. 7. if the minimum horizontal clock low level is used (?5.2 v), then the maximum horizontal clock amplitude should be used (5.2 v a mplitude) to create a ?5.2 v to 0.0 v clock. if a 5 v clock driver is used, the horizontal low level should be set to ?5.0 v and the high lev el should be a set to 0.0 v.
kai ? 01150 www.onsemi.com 24 the figure below shows the dc bias (vsub) and ac clock (ves) applied to the sub pin. both the dc bias and ac clock are referenced to ground. figure 21. dc bias and ac clock applied to the sub pin vsub ves gnd gnd device identification the device identification pin (devid) may be used to determine which on semiconductor 5.5 micron pixel interline ccd sensor is being used. table 21. description pins symbol min. nom. max. unit max. dc current notes device identification devid devid 4,000 5,000 6,000 50 a 1, 2, 3 1. nominal value subject to verification and/or change during release of preliminary specifications. 2. if the device identification is not used, it may be left disconnected. 3. after device identification resistance has been read during camera initialization, it is recommended that the circuit be disa bled to prevent localized heating of the sensor due to current flow through the r_deviceid resistor. recommended circuit note that v1 must be a different value than v2. figure 22. device identification recommended circuit adc r_external v1 v2 devid gnd kai ? 02150 r_deviceid
kai ? 01150 www.onsemi.com 25 timing table 22. requirements and characteristics description symbol min. nom. max. unit notes photodiode transfer t pd 1.0 ? ? s vccd leading pedestal t 3p 4.0 ? ? s vccd trailing pedestal t 3d 4.0 ? ? s vccd transfer delay t d 1.0 ? ? s vccd transfer t v 1.0 ? ? s vccd clock cross-over v vcr 75 ? 100 % 2 vccd rise, fall times t vr , t vf 5 ? 10 % 2, 3 hccd delay t hs 0.2 ? ? s hccd transfer t e 25.0 ? ? ns shutter transfer t sub 1.0 ? ? s shutter delay t hd 1.0 ? ? s reset pulse t r 2.5 ? ? ns reset ? video delay t rv ? 2.2 ? ns h2sl ? video delay t hv ? 3.1 ? ns line time t line 19.0 ? ? s dual hccd readout 36.1 ? ? single hccd readout frame time t frame 7.2 ? ? ms quad hccd readout 14.5 ? ? dual hccd readout 26.8 ? ? single hccd readout 1. refer to timing diagrams as shown in figure 23, figure 24, figure 25, figure 26 and figure 27. 2. refer to figure 27: vccd clock rise time, fall time and edge alignment 3. relative to the pulse width.
kai ? 01150 www.onsemi.com 26 timing diagrams the timing sequence for the clocked device pins may be represented as one of seven patterns (p1 ? p7) as shown in the table below. the patterns are defined in figure 23 and figure 24. contact on semiconductor application engineering for other readout modes. table 23. timing diagrams device pin quad readout dual readout vouta, voutb dual readout vouta, voutc single readout vouta v1t p1t p1b p1t p1b v2t p2t p4b p2t p4b v3t p3t p3b p3t p3b v4t p4t p2b p4t p2b v1b p1b v2b p2b v3b p3b v4b p4b h1sa p5 h1ba p5 h2sa (note 2) p6 h2ba p6 ra p7 h1sb p5 p5 h1bb p5 p6 h2sb (note 2) p6 p6 h2bb p6 p5 rb p7 p7 (note 1) or off (note 3) p7 (note 1) or off (note 3) h1sc p5 p5 (note 1) or off (note 3) p5 p5 (note 1) or off (note 3) h1bc p5 p5 (note 1) or off (note 3) p5 p5 (note 1) or off (note 3) h2sc (note 2) p6 p6 (note 1) or off (note 3) p6 p6 (note 1) or off (note 3) h2bc p6 p6 (note 1) or off (note 3) p6 p6 (note 1) or off (note 3) rc p7 p7 (note 1) or off (note 3) p7 p7 (note 1) or off (note 3) h1sd p5 p5 (note 1) or off (note 3) p5 p5 (note 1) or off (note 3) h1bd p5 p5 (note 1) or off (note 3) p6 p5 (note 1) or off (note 3) h2sd (note 2) p6 p6 (note 1) or off (note 3) p6 p6 (note 1) or off (note 3) h2bd p6 p6 (note 1) or off (note 3) p5 p6 (note 1) or off (note 3) rd p7 p7 (note 1) or off (note 3) p7 (note 1) or off (note 3) p7 (note 1) or off (note 3) #lines/frame (minimum) 380 760 380 760 #pixels/line (minimum) 693 1386 1. for optimal performance of the sensor. may be clocked at a lower frequency. if clocked at a lower frequency, the frequency se lected should be a multiple of the frequency used on the a and b register. 2. h2slx follows the same pattern as h2sx for optimal speed performance, use a separate clock driver. 3. off = +5 v. note that there may be operating conditions (high temperature and/or very bright light sources) that will cause bl ooming from the unused c/d register into the image area.
kai ? 01150 www.onsemi.com 27 photodiode transfer timing a row of charge is transferred to the hccd on the falling edge of v1 as indicated in the p1 pattern below. using this timing sequence, the leading dummy row or line is combined with the first dark row in the hccd. the ?last line? is dependent on readout mode ? either 380 or 760 minimum counts required. it is important to note that, in general, the rising edge of a vertical clock (patterns p1 ? p4) should be coincident or slightly leading a falling edge at the same time interval. this is particularly true at the point where p1 returns from the high (3 rd level) state to the mid-state when p4 transitions from the low state to the high state. figure 23. photodiode transfer timing last line l1 + dummy line p1b p2b p3b p4b pattern l2 p1t p2t p3t p4t t v t v /2 t pd t v /2 t v /2 t d t d t 3p t 3d t v t hs t v t v /2 t v t hs t v /2 t v /2 p5 p6 p7 1 2 3 4 5 6 line and pixel timing each row of charge is transferred to the output, as illustrated below , on the falling edge of h2sl (indicated as p6 pattern). the number of pixels in a row is dependent on readout mode ? either 693 or 1386 minimum counts required. figure 24. line and pixel timing p1t p5 p6 p7 pixel n pixel 1 pixel 34 t line t v t hs t e t r t e /2 vout pattern p1b t v
kai ? 01150 www.onsemi.com 28 pixel timing detail figure 25. pixel timing detail p5 p6 p7 vout t hv t rv frame/electronic shutter timing the sub pin may be optionally clocked to provide electronic shuttering capability as shown below. the resulting photodiode integration time is defined from the falling edge of sub to the falling edge of v1 (p1 pattern). figure 26. frame/electronic shutter timing p1t/b p6 sub t int t frame t hd t hd t sub pattern vccd clock rise time, fall time and edge alignment figure 27. vccd clock rise time, fall time and edge alignment v vcr 90% 10% t vf t vr t v t v t vf t vr
kai ? 01150 www.onsemi.com 29 line and pixel t iming ? vertical binning by 2 figure 28. line and pixel timing ? vertical binning by 2 p1t p2t p3t p4t p1b p2b p3b p4b p5 p6 p7 vout pixel n pixel 34 pixel 1 t v t v t v t hs t hs
kai ? 01150 www.onsemi.com 30 storage and handling table 24. storage conditions description symbol minimum maximum units notes storage temperature t st ? 55 80 c 1 humidity rh 5 90 % 2 1. long-term storage toward the maximum temperature will accelerate color filter degradation. 2. t = 25 c. excessive humidity will degrade mttf. for information on esd and cover glass care and cleanliness, please download the image sensor handling and best practices application note (an52561/d) from www.onsemi.com . for information on environmental exposure, please download the using interline ccd image sensors in high intensity lighting conditions application note (and9183/d) from www.onsemi.com . for information on soldering recommendations, please download the soldering and mounting techniques reference manual (solderrm/d) from www.onsemi.com . for quality and reliability information, please download the quality & reliability handbook (hbd851/d) from www.onsemi.com . for information on device numbering and ordering codes, please download the device nomenclature technical note (tnd310/d) from www.onsemi.com . for information on standard terms and conditions of sale, please download terms and conditions from www.onsemi.com .
kai ? 01150 www.onsemi.com 31 mechanical information pga completed assembly figure 29. pga completed assembly 1. see ordering information for marking code. 2. no materials to interfere with clearance through guide holes. 3. the center of the active image is nominally at the center of the package. 4. die rotation < 0.5 degrees. 5. glass rotation < 1.5 degrees 6. internal traces may be exposed on sides of package. do not allow metal to contact sides of ceramic package. 7. recommended mounting screws: a.) 1.6 0.35 mm (iso standard) b.) 0?80 (unified fine thread standard). 8. units: in [mm] notes:
kai ? 01150 www.onsemi.com 32 clcc completed assembly figure 30. clcc completed assembly 1. see ordering information for marking code. 2. die rotation < 0.5 degrees. 3. units: millimeters. notes:
kai ? 01150 www.onsemi.com 33 pga cover glass figure 31. pga cover glass 1. dust/scratch count ? 12 micron maximum 2. units: in [mm] 3. reflectance specification a. 420 nm to 435 nm < 2.0% b. 435 nm to 630 nm < 0.8% c. 630 nm to 680 nm < 2.0% notes:
kai ? 01150 www.onsemi.com 34 clcc cover glass figure 32. clcc cover glass 1. dust/scratch count ? 12 micron maximum 2. units: millimeter 3. reflectance specification a. 420 nm to 435 nm < 2.0% b. 435 nm to 630 nm < 0.8% c. 630 nm to 680 nm < 2.0% notes:
kai ? 01150 www.onsemi.com 35 pga clear cover glass figure 33. pga clear cover glass 1. dust/scratch count ? 12 micron maximum 2. units: in notes:
kai ? 01150 www.onsemi.com 36 cover glass transmission figure 34. cover glass transmission note: pga and clcc mar transmission data differ due to in-spec differences from glass vendor. 0 10 20 30 40 50 60 70 80 90 100 200 300 400 500 600 700 800 900 transmission (%) wavelength (nm) pga mar clcc mar pga clear on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warrant y, representation or guarantee regarding the suitability of it s products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 kai ? 01150/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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